The present invention relates to CAM (Content Addressable Memory) and more particularly to a semiconductor integrated circuit having a CAM structure comprising newly formed cells based on a nonvolatile memory element.
Heretofore, fully parallel CAMs (Content Addressable Memories), which are also called associative memories, have been widely known as semiconductor memory circuits having the functions of performing the match (or coincident) detection of between retrieval data and stored data concurrently in terms of all bits and outputting the match address of stored data or stored data (see "Design of CMOS VLSI," pp 176-177, edited by Tetsuya Iizuka and supervised by Takuo Sugano, Baifukan, 1989).
However, the bitwise configuration of a typical conventional CAM comprising SRAM cells and exclusive NOR circuits has made it impossible to provide CAM having a large-sized cell and consequently a capacity at a level fit for practical use.
In many IC cards that have recently been commercialized as personal data bases, for instance, no CAM has been arranged as stated above. In such an IC card, an arrangement has been made to find out data for the intended purpose by sequentially retrieving data one after another from ROM (Read Only Memory) in which the data are prestored. For this reason, the greater the number of data becomes, as in language dictionaries such as Japanese and English-Japanese dictionaries, the more it requires time to retrieve data. In other words, what has high-speed, flexible retrieval functions is still nonexistent.
If all data are made retrievable at a time as in the case of CAM, not by retrieving data one by one with the aid of software from the conventional ROM and the like in the prior art as stated above, data retrieval from the IC card equipped with a large memory capacity may be implemented with flexibility at high speed.
U.S. Pat. No. 3,701,980 (October 1972) and Japanese Patent Laid-Open No. 194196/1989, for instance, suggest the possibility of large capacity associative memories. The former U.S. patent is based on DRAM having a CAM cell structure with ordinary 2-bit memories as one set, whereas the latter is based on an EPROM nonvolatile memory, also forming CAM having one set of ordinary 2-bit EPROM memories. Consequently, both can be subjected to integration larger in scale than that of CAM based on SRAM.
Notwithstanding, what is based on DRAM disclosed in U.S. Pat. No. 3,701,980 still poses a problem in view of its area size. In the case of the associative memory based on EPROM as a nonvolatile memory, which is disclosed in Japanese Patent laid-open No. 194196/1989, flexible write/read is impossible in that EPROM with two bits as one set is structurally employed to make ground lines for common use match lines and that no attentive consideration has been given to particulars of retrieval operation.